`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   11:00:34 12/03/2011
// Design Name:   VGAController
// Module Name:   C:/Users/Tyson/Documents/Verilog Projects/Cs3710/16bitcpu/VGAController_simulation.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: VGAController
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module VGAController_simulation;

	// Inputs
	reg clk;
	reg invert;
	reg reset;
	reg [11:0] plyr_input;
	reg [11:0] plyr2_input;
	reg [3:0] tile;
	reg draw_enable;
	reg [9:0] objXStart;
	reg [8:0] objYStart;

	// Outputs
	wire vga_h_sync;
	wire vga_v_sync;
	wire [2:0] R;
	wire [2:0] G;
	wire [1:0] B;
	wire [9:0] CounterX;
	wire [8:0] CounterY;

	// Instantiate the Unit Under Test (UUT)
	VGAController uut (
		.clk(clk), 
		.invert(invert), 
		.reset(reset), 
		.plyr_input(plyr_input), 
		.plyr2_input(plyr2_input), 
		.vga_h_sync(vga_h_sync), 
		.vga_v_sync(vga_v_sync), 
		.R(R), 
		.G(G), 
		.B(B), 
		.CounterX(CounterX), 
		.CounterY(CounterY), 
		.tile(tile), 
		.draw_enable(draw_enable), 
		.objXStart(objXStart), 
		.objYStart(objYStart)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		invert = 0;
		reset = 0;
		plyr_input = 0;
		plyr2_input = 0;
		tile = 0;
		draw_enable = 0;
		objXStart = 0;
		objYStart = 0;

		// Wait 100 ns for global reset to finish
		#100;
       reset = 1;
		 #50;
		 reset  = 0;
		 #5;
		 draw_enable = 1;
		 #1;
		 plyr_input = 1;
		 #50;
		 plyr_input = 2;
		 #50;
		 plyr_input = 4;
		 #50;
		 plyr_input = 0;
		 #50;
		 plyr2_input = 2;
		// Add stimulus here
 
	end
      
		always begin
		#1; clk = !clk;
		end
endmodule

